High-Speed IO
112G SerDes Lane
Impedance-controlled SerDes lane layout with shielded differential routing and full ESD compliance.
- Node
- 7nm
- Technology
- 7nm FinFET
- Discipline
- High-Speed IO
Engineering Highlights
- Length and impedance matched differential pairs
- Shielded routing with continuous return path
- Lane tiling for multi-channel assembly
