What we have learned, written down
Practical notes from the layout and physical design work we do every day, plus the whitepapers and answers customers ask for most.
Engineering notes
- AMS Layout8 min
Matching Strategies That Survive Advanced Nodes
Common-centroid still works at 5nm, but only if the dummy strategy and orientation rules are handled deliberately.
- RF / mmWave6 min
Why Your mmWave Inductor Q Drops in Silicon
Five layout decisions that quietly cost you quality factor, and how EM verification catches each one.
- Physical Design7 min
Congestion Is a Floorplan Problem
By the time the router complains, the decision that caused it was made weeks earlier. Here is where to look.
Longer-form methodology
Parasitic-Aware Analog Layout at 5nm and Below
A practical methodology for closing the gap between schematic intent and extracted silicon behaviour.
18 pagesAutomating Array Layout with SKILL Generators
How parameterized generators reduce turnaround on capacitor, resistor and bitcell arrays.
14 pagesA Sign-off Checklist for First-Pass Silicon
The verification gates we run before a database is considered release ready.
11 pages
Short technical notes
Reliability Verification with Calibre PERC in Automotive Flows
Technical NoteUseful Skew as a Power Optimization Lever
Technical NotePorting Analog IP Across Foundries Without Respinning
Technical Note
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Questions we get asked most
Fixed-scope project delivery, dedicated offshore teams and time-and-materials augmentation of your existing team. Most customers start with a scoped pilot block before scaling.
TSMC, Samsung, GlobalFoundries, Intel Foundry, UMC, SMIC, X-FAB, Tower, SilTerra and Renesas, from 250nm mature processes through to 2nm advanced nodes.
Every engagement runs under NDA on segregated project infrastructure with access control per project. We can work inside your environment over VPN or VDI where required.
Yes. We begin with a database and methodology audit, document the current state and gaps, then agree a recovery plan before taking execution ownership.
A representative analog block is usually two to four weeks depending on complexity and node, including verification and a review cycle.
Yes. We support silicon debug, ECO cycles and derivative respins, and retain project databases and documentation for the agreed term.