Physical Design
5nm High-Performance SoC
Advanced digital SoC with complex analog IP integration, closed for timing and power on a tight tapeout schedule.
- Node
- 5nm
- Technology
- 5nm TSMC
- Discipline
- Physical Design
Engineering Highlights
- Hierarchical floorplan across 9 physical partitions
- Multi-corner multi-mode timing closure
- IR drop held within 4% of nominal supply
