Team

Our Team

The team boasts over 45+ years of collective expertise in designing Low-power custom Digital, High-frequency Analog, and Mixed-signal IC within cutting-edge fabrication processes technology.

Analog Circuit Design Engineer

Our seasoned engineers have more than Sixteen (16) years of extensive experience in analog, mixed-signal, and RF IC design with a Ph.D. in Electronic Engineering and a proven track record in industrial and academic Research and development activities, rigorous experience with different CMOS/BiCMOS technologies, and a good understanding of circuit and systems.

Core Competencies

Rigorous experience with CMOS 65nm, 90nm, 130nm, 180nm; BiCMOS 0.5um; FinFET 3nm, 7nm, 10nm, 14nm; and FDX 22nm nodes
Opamp, comparator, bias circuits, bandgap, LNA, PLL, SAL, SERDES receiver, Sigma-Delta converter design
DC-DC systems (SMPS/LDOs) design
Low-power RF Transmitter and Receiver design
Spectre/HSpice: Schematic composition and simulation
Understanding of RTL design and validation
Post-silicon test and debug

Tools Expertise

Cadence® Virtuoso Schematic Editor, Spectre, NC-Verilog.
HSpice
Cohesion Designer
MATLAB
Mentor Graphics Calibre
Dolphin® SLED, SMASH
Microwave Studio
Origin

Custom IC Layout Design Engineer

Our Seasoned engineers have more than Ten (10) years of experience and have successfully implemented high-quality full-custom layouts of high-performance arrays, memory, RF/mmWave, and analog circuits for semiconductor manufacturing companies by following strict guidelines for performance and reliability and also demonstrated excellence in the layout of leaf cells, library development, and physical design verification.

Analog Layout Design
Digital Layout Design
RF/mmWave Layout Design

Core Competencies

Expertise with FinFET 5nm, 7nm, 10nm, 14nm, and 16nm; FDX 22nm, CMOS 22nm, 28nm, 40nm, 45nm, and 180nm; BCD 90nm and 180nm nodes
Analog circuit layout: 3DNAND and NOR Flash Memory, PMIC, MCU, ADC, LDO, High Voltage Regulator, OPAMP, Charge Pump, PLL, Level Shifter, GPIO, ESD and Clamp design
RF/mmWave circuit layout: AD/DA Converters, BGR, Fast Low Noise Amplifier, Power Detector, Power Amplifier, Phase Shifter, Bias Generator, Comparator, Inductor, Voltage Level Shifter, Switches and Constant Current Generator design
Custom SRAM circuit layout: Bit Cells, Array, SenseAmp, Controller, Driver, Data Path and IO design
Chip-level floor planning, block integration, PAD, GPIO, seal ring placement, core wiring, analog and digital IP isolation, ESD protection, RDL metal uses, sensitive clock noisy signal flow drawing, and power distribution with star connections
Physical and reliability verification flows
FILL, LEF, abstract generation, and layout to GDS/GDS to layout conversion
SLM and Test Structure layout design and verification

Tools Expertise

Cadence Virtuoso L, XL, EXL and GXL
Cadence PVS and ASSURA Verification Flow
Mentor Graphics Calibre Verification Flow
Synopsys Hercules Verification Flow
ClioSoft, IC Manage Revision Control
Atlassian Jira Ticketing and Project Management

Physical Design Engineer

More than Twelve (12) years of proven experience specializing in physical design implementation of high-performance ASICs. Working experience on multiple projects from RTL to GDSII in 3nm-180nm technology, including advanced FinFET process nodes.

Core Competencies

Design Automation in TCL, Python, Perl
Complex Partition Timing and DRC convergence
Full Chip Floorplan and Integration with Design Planning experience
Complex clock tree synthesis on skew and latency target meet up
Early planning in floorplan, placement and CTS to have lesser ECO cycle
Timing, Power Constraint debugging skill with early cleanup
Multi-voltage Implementation issue resolving
40+ successful Tape out experience
Front end and DFT related good understanding to close gap

Tools Expertise

INNOVUS
ICC2
APRISA
IPVS
VOLTUS
TEMPUS
PRIMETIME
GENUS
FUSION COMPILER
INCISIVE
MODUS
CONFORMAL
Calibre LVS/DRC

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